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specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 30712hkpc 20120113-s00002,s00003 no.a2000-1/14 LC74900 overview LC74900 is a highly integrated multi-purpose lcd panel (up to wvga) controller processing analog and digital video signal. it contains a/d converter, video decorder, de-interlacer/scaler, an d picture improvement. features (1) video input/output ? analog input: 4ch cvbs (ntsc, pal, and secam) with 1ch 10bit a/d converter ? digital input: 24bit rgb and ycbcr, 16bit ycbcr (4:2:2), and 8bit yc (bt.656) ? digital output: 8bit video decoder output (bt.656) (2) yc separation video decoder ? adaptive 3line comb filter, automatic gain and chrominance control (3) de-interlacer and scaler ? horizontal and vertical programm able scaler separately, and supports panels up to wvga resolutions (4) picture improvements ? cdex (color depth expander): high quality expansion for low-resolution graphics ? dynamic gamma correction: picture adapted automatic luminance control ? sharpness control, lti and cti: peaking enhancement without glares ? color exciter: 6 phases rgbymc gain control separately (5) panel interface ? 24bit rgb output and 18bit rgb output with dithering process ? pulse width modulation for automatic led backlight control ? timing conroller for lcd driver with horizontal or vertical reversing signals ? pin swapping : replace output pin a ssignment of the rgb channel or bit continued on next page. cmos ic silicon gate lcd processor lsi for small size display orderin g numbe r : ena2000
LC74900 no.a2000-2/14 continued from preceding page. (6) on screen display ? built-in osd controller with integrated font rom, which contains 501 fonts, and fomt ram, which contains 8 fonts ? character numbers displayed on the screen: 24 characters by 8 rows, 24 characters by 10 rows, or 32 characters by 8 rows ? character size: 16 pixels wide by 20 pixels high ? character colors: 8 font colors for eac h character, 8 back colors for each character, and 8 font border colors for each row ? inverting font colors and back colors each character , blinking fonts each charact er, and fringing each row ? pin assignment for an optional external osd controller: 24bit, 18bit, 12bit, and 6bit rgb (7) eeprom booting ? quick boot from an external eeprom in power on sequence before starting a system controller ? waiting timer between data transfers ? verifying boot datas ? eeprom size: up to 512k bits with i 2 c or spi interface (8) parallel data outputs, panel in terface and video decorder output ? reentering video decoder outputs, which are processed by an external graphic engine as digital inputs (9) system controller interface ? spi (max 1mbit/s) or i 2 c bus (100kbit/s or 400kbit/s) lsi specification ? supply voltage: 1.5v (core), 3.3v (io) ? maximum operation frequency: 60mhz (video processing) ? package: 120pin tqfp applications ? for mediam or small size lcd panel ? automobile use: car tv, portable navigation, etc. ? home use: photo frame, port able dvd, door phone, etc.
LC74900 no.a2000-3/14 specifications absolute maximum ratings at ta = 25 c, dv ss = 0v, adc0av ss = 0v, adc1av ss = 0v, pllav ss = 0v, xv ss = 0v parameter symbol conditions ratings unit maximum supply voltage (i/o) dv dd 33 xv dd 33 dv dd 3318 -0.3 to +3.96 v maximum supply voltage (analog) adc0av dd 33 adc1av dd 33 pllav dd 33 -0.3 to +3.96 v maximum supply voltage (core) dv dd 15 -0.3 to +1.8 v -0.3 to dv dd 33+0.3 v i -0.3 to dv dd 3318+0.3 digital input voltage v i (5v tolerant) -0.3 to +5.6 v -0.3 to dv dd 33+0.3 digital output voltage v o -0.3 to dv dd 3318+0.3 v maximum allowable loss pd max ta = 85 c, with evaluation board* 0.7 w operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c *: board size: 150mm 150mm 1.6mm, fr-4, 6layers allowable operation ranges at ta = -40 to +85 c, dv ss = 0v, adc0av ss = 0v, adc1av ss = 0v, pllav ss = 0v, xv ss = 0v parameter symbol conditions min typ max unit dv dd 33 xv dd 33 3.15 3.3 3.45 v 3.15 3.3 3.45 v supply voltage (i/o) dv dd 3318 1.7 1.8 1.9 v supply voltage (analog) adc0av dd 33 adc1av dd 33 pllav dd 33 3.15 3.3 3.45 v supply voltage (core) dv dd 15 1.4 1.5 1.6 v input voltage range v in 0 dv dd 33 dv dd 3318 v input voltage range (5v tolerant) v in 5 0 5.5v
LC74900 no.a2000-4/14 dc characteristics at ta = -40 to +85 c, dv ss = 0v, adc0av ss = 0v, adc1av ss = 0v, pllav ss = 0v, xv ss = 0v, dv dd 33 = 3.15v to 3.45v, dv dd 3318 = 3.15v to 3.45v or 1.7v to 1.9v, dv dd 15 = 1.42v to 1.58v, xv dd 33 = 3.15v to 3.45v, adc0av dd = 3.15v to 3.45v, adc1av dd = 3.15v to 3.45v, pllav dd = 3.15v to 3.45v parameter symbol conditions min typ max unit cmos level inputs 0.7dv dd 33 0.7dv dd 3318 v input high-level voltage v ih cmos level schmitt inputs 0.7dv dd 33 v cmos level inputs 0 0.3dv dd 33 0.3dv dd 3318 v input low-level voltage v il cmos level schmitt inputs 0 0.3dv dd 33 v v i = dv dd 33 a input high-level current i ih v i = dv dd 3318 a input low-level current i il v i = dv ss a type b: i oh = -4ma type g: i oh = -6ma dv dd 33-0.6 v dvdd3318 = 3.15v to 3.45v type j: i oh = -4ma type k: i oh = -6ma dv dd 3318-0.6 v output high-level voltage v oh dvdd3318 = 1.7v to 1.9v type j: i oh = -3ma type k: i oh = -5ma dv dd 3318-0.4 v output low-level voltage v ol cmos 0.4 v output leakage current i oz when in high-impedance output mode -10 10 a output open, tck = 9mhz, 10steps ta = 25 c, dv dd 33 = 3.3v, dv dd 3318 = 3.3v, xv dd = 3.3v, dv dd 15 = 1.5v, adc0av dd = 3.3v, adc1av dd = 3.3v, pllav dd = 3.3v 95 ma operating current drain i ddop output open, tck = 33mhz, 10steps ta = 25 c, dv dd 33 = 3.3v, dv dd 3318 = 3.3v, xv dd = 3.3v, dv dd 15 = 1.5v, adc0av dd = 3.3v, adc1av dd = 3.3v, pllav dd = 3.3v 139 ma static current drain i ddst output open, tck: stop v i = dv ss , ta = 25 c, dv dd 33 = 3.3v, dv dd 3318 = 1.8v, xv dd = 3.3v, dv dd 15 = 1.5v, adc0av dd = 3.3v, adc1av dd = 3.3v, pllav dd = 3.3v 34 a
LC74900 no.a2000-5/14 package dimensions unit : mm (typ) 3257a sanyo : tqfp120(14x14) 0.125 120 0.15 0.4 (1.2) 1 14.0 16.0 14.0 16.0 1.2max 0.1 (1.0) 0.5
LC74900 no.a2000-6/14 pin assignment dv dd 15 xrst xpdwn gp0 gp1 gp2 dv dd 33 dv ss sck_scl srxd_sda stxd scs_i2sel siosel mode2 mode3 test refpkv vrt refnkv vrb adc0av dd 33 ain4 adc0av ss 33 ain3 adc1av dd 33 ain2 adc1av ss 33 ain1 svo lpfo pllav dd 33 pdo pllav ss 33 xv dd 33 xtali xtalo xv ss dv dd 15 mode0 dcki mode1 xmute into ddei dvsi dhsi dv dd 33 dcbin0 dcbin1 dcbin2 dcbin3 dcbin4 dcbin5 dv ss dcbin6 dcbin7 dygin0 dygin1 dygin2 dygin3 5 10 15 20 25 30 35 40 45 50 55 60 top view LC74900 90 85 80 75 70 65 120 115 110 105 100 95 dgout3 dgout2 dgout1 dgout0 dbout7 dbout6 dv dd 33 dbout5 dbout4 dbout3 dbout2 dbout1 dv dd 15 dbout0 drout7 drout6 drout5 drout4 dv ss dcko1 dv dd 33 drout3 drout2 drout1 drout0 dv ss dygin7 dygin6 dygin5 dygin4 dcrin7 dcrin6 dcrin5 dcrin4 dv ss dcko2 dv dd 3318 dcrin3 dcrin2 dcrin1 dcrin0 dv dd 15 grst flm oe cpv strb sp dv dd 33 pol pwm dexr ddeo dvso dv ss dhso dgout7 dgout6 dgout5 dgout4
LC74900 no.a2000-7/14 block diagram LC74900 de-interlacer & scaler picture quality improvement osd mix tcon dhso/sp2 dvso/flm2 ddeo dcko grst flm oe cpv strb sp dexr pol panel protection xrst srxd_sda scs _ i2sel spi/ i 2 c stxd sck _ scl pll xtalo xtali 1ch 10bit adcs & afe video decoder mux ain1 ain2 ain3 ain4 pwm pwm into dgout[7:0] dbout[7:0] drout[7:0] osd lcd back light controler mpu timing controler mux dhsi dvsi ddei dcki dygin[7:0] dcbin[7:0] dcrin[7:0] eeprom xmute
LC74900 no.a2000-8/14 pin functions i/o format pin no. pin symbol i/o format connected to digital io power supply remarks 1 dv dd 15 p - core voltage digital power supply for core (1.5v) 2 xrst i a cmos digital dv dd 33 reset pin (active at a low voltage level) 3 xpdwn i a cmos digital dv dd 33 fixed at a high voltage level 4 gp0 i/o b cmos digital dv dd 33 input: digital input/osd enable (pull down if not used) output: global port/video decoder vsync 5 gp1 i/o b cmos digital dv dd 33 input: digital input/osd halftone (pull down if not used) output: global port/video decoderhsync 6 gp2 i/o b cmos digital dv dd 33 global port output 7 dv dd 33 p - io voltage digital power supply for io (3.3v) 8 dv ss p - gnd digital gnd for digital 9 sck_scl i/o c cmos digital dv dd 33 i 2 c: i 2 c clock inout, spi: clock input 10 srxd_sda i/o c cmos digital dv dd 33 i 2 c: data inout, spi: data input 11 stxd i/o b cmos digital dv dd 33 spi: data output 12 scs_i2sel i a cmos digital dv dd 33 i 2 c: select i 2 c slave address, spi: chip select 13 siosel i d cmos digital dv dd 33 select cpu i/f, ?l?: i 2 c, ?h?: spi 14 mode2 i d cmos digital dv dd 33 operation mode control 15 mode3 i d cmos digital dv dd 33 operation mode control 16 test i d cmos digital dv dd 33 for production test (fixed at a low voltage level) 17 refpkv i e analog top reference level buffer-amp input for adc 18 vrt i e analog top reference level for adc 19 refnkv i e analog bottom reference level buffer-amp input for adc 20 vrb i e analog bottom reference level for adc 21 adc0av dd 33 p - analog voltage analog power supply for adc (3.3v) 22 ain4 i e analog cvbs input 4 23 adc0av ss 33 p - gnd analog gnd for adc 24 ain3 i e analog cvbs input 3 25 adc1av dd 33 p - analog voltage analog power supply for adc (3.3v) 26 ain2 i e analog cvbs input 2 27 adc1av ss 33 p - gnd analog gnd for adc 28 ain1 i e analog cvbs input 1 29 svo o e analog afe output 30 lpfo o e analog external agc control level 31 pllav dd 33 p - analog voltage analog power supply for pll (3.3v) 32 pdo o - analog test port for pll (open) 33 pllav ss 33 p - gnd analog gnd for pll 34 xv dd 33 p - io voltage digital power supply for 27mhz x?tal (3.3v) 35 xtali i f cmos digital xv dd 33 27mhz x?tal input 36 xtalo o f cmos digital xv dd 33 27mhz x?tal output 37 xv ss p - gnd digital gnd for 27mhz x?tal 38 dv dd 15 p - core voltage digital power supply for core (1.5v) 39 mode0 i d cmos digital dv dd 33 operation mode control 40 dcki i d cmos digital dv dd 33 digital video clock 41 mode1 i d cmos digital dv dd 33 operation mode control 42 xmute i a cmos digital dv dd 33 mute control (active at a low voltage level) 43 into i/o b cmos digital dv dd 33 interrupt output 44 ddei i d cmos digital dv dd 33 digital video enable/osd enable 45 dvsi i d cmos digital dv dd 33 digital video vsync/osd half tone 46 dhsi i d cmos digital dv dd 33 digital video hsync 47 dv dd 33 p - io voltage digital power supply for io (3.3v) 48 dcbin0 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 49 dcbin1 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 50 dcbin2 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) continued on next page.
LC74900 no.a2000-9/14 continued from preceding page. i/o format pin no. pin symbol i/o format connected to digital io power supply remarks 51 dcbin3 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 52 dcbin4 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 53 dcbin5 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 54 dv ss p gnd digital gnd for digital 55 dcbin6 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 56 dcbin7 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 57 dygin0 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 58 dygin1 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 59 dygin2 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 60 dygin3 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 61 dygin4 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 62 dygin5 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used)) 63 dygin6 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 64 dygin7 i d cmos digital dv dd 33 digital video input/osd input (pull down if not used) 65 dv ss p gnd digital gnd for digital 66 drout0 i/o b cmos digital dv dd 33 panel r output (lsb) (input port in test mode) 67 drout1 i/o b cmos digital dv dd 33 panel r output (input port in test mode) 68 drout2 i/o b cmos digital dv dd 33 panel r output (input port in test mode) 69 drout3 i/o b cmos digital dv dd 33 panel r output (input port in test mode) 70 dv dd 33 p io voltage digital power supply for io (3.3v) 71 dcko1 o g cmos digital dv dd 33 panel clock output 72 dv ss p gnd digital gnd for digital 73 drout4 i/o b cmos digital dv dd 33 panel r output (input port in test mode) 74 drout5 i/o b cmos digital dv dd 33 panel r output (input port in test mode) 75 drout6 i/o b cmos digital dv dd 33 panel r output (input port in test mode) 76 drout7 i/o b cmos digital dv dd 33 panel r output (msb) (input port in test mode) 77 dbout0 i/o b cmos digital dv dd 33 panel b output (lsb) (input port in test mode) 78 dv dd 15 p core voltage digital power supply for core (1.5v) 79 dbout1 i/o b cmos digital dv dd 33 panel b output (input port in test mode) 80 dbout2 i/o b cmos digital dv dd 33 panel b output (input port in test mode) 81 dbout3 i/o b cmos digital dv dd 33 panel b output (input port in test mode) 82 dbout4 i/o b cmos digital dv dd 33 panel b output (input port in test mode) 83 dbout5 i/o b cmos digital dv dd 33 panel b output (input port in test mode) 84 dv dd 33 p io voltage digital power supply for io (3.3v) 85 dbout6 i/o b cmos digital dv dd 33 panel b output (input port in test mode) 86 dbout7 i/o b cmos digital dv dd 33 panel b output (msb) (input port in test mode) 87 dgout0 i/o b cmos digital dv dd 33 panel g output (lsb) (input port in test mode) 88 dgout1 i/o b cmos digital dv dd 33 panel g output (input port in test mode) 89 dgout2 i/o b cmos digital dv dd 33 panel g output (input port in test mode) 90 dgout3 i/o b cmos digital dv dd 33 panel g output (input port in test mode) 91 dgout4 i/o b cmos digital dv dd 33 panel g output (input port in test mode) 92 dgout5 i/o b cmos digital dv dd 33 panel g output (input port in test mode) 93 dgout6 i/o b cmos digital dv dd 33 panel g output (input port in test mode) 94 dgout7 i/o b cmos digital dv dd 33 panel g output (msb) (input port in test mode) 95 dhso i/o b cmos digital dv dd 33 panel hsync/start pulse for source driver/ video decoder vsync output (input port in test mode) 96 dv ss p gnd digital gnd for digital 97 dvso i/o b cmos digital dv dd 33 panel vsync/start pulse for gate driver/ video decoder vsync output (input port in test mode) 98 ddeo i/o b cmos digital dv dd 33 panel enable output (input port in test mode) 99 dexr i/o b cmos digital dv dd 33 invert control signal for dtr/ video decorer output 1[7](bt.656) (input port in test mode) continued on next page.
LC74900 no.a2000-10/14 continued from preceding page. i/o format pin no. pin symbol i/o format connected to digital io power supply remarks 100 pwm i/o b cmos digital dv dd 33 pulse width modulation (input port in test mode) 101 pol i/o b cmos digital dv dd 33 polarity control for source driver/ video decoder output 1[6] (bt.656) (input port in test mode) 102 dv dd 33 p io voltage digital power supply for io (3.3v) 103 sp i/o b cmos digital dv dd 33 start pulse for source driver/ video decoder output 1[5] (bt.656) (input port in test mode) 104 strb i/o b cmos digital dv dd 33 data stroboscope for source driver/ video decoder output 1[4] (bt.656) (input port in test mode) 105 cpv i/o b cmos digital dv dd 33 clock for gate driver/ video decoder output 1[3] (bt.656) (input port in test mode) 106 oe i/o b cmos digital dv dd 33 output enable for gate driver/ video decoder output 1[2] (bt.656) (input port in test mode) 107 flm i/o b cmos digital dv dd 33 start pulse for gate driver/ video decoder output 1[1] (bt.656) (input port in test mode) 108 grst i/o b cmos digital dv dd 33 reset for gate driver/ video decoder output1[0] (bt.656) (input port in test mode) 109 dv dd 15 p core voltage digital power supply for core (1.5v) 110 dcrin0 i/o h cmos digital dv dd 3318 input: digital video input/osd input (pull down if not used) output: video decoder output 2[0] (bt.656) 111 dcrin1 i/o h cmos digital dv dd 3318 input: digital video input/osd input (pull down if not used) output: video decoder output 2[1] (bt.656) 112 dcrin2 i/o h cmos digital dv dd 3318 input: digital video input/osd input (pull down if not used) output: video decoder output 2[2] (bt.656) 113 dcrin3 i/o h cmos digital dv dd 3318 input: digital video input/osd input (pull down if not used) output: video decoder output 2[3] (bt.656) 114 dv dd 3318 p - io voltage digital power supply for io (3.3v/1.8v) 115 dcko2 o j cmos digital dv dd 3318 video decoder clock output 116 dv ss p - gnd digital gnd for digital 117 dcrin4 i/o h cmos digital dv dd 3318 input: digital video input/osd input (pull down if not used) output: video decoder output 2[4] (bt.656) 118 dcrin5 i/o h cmos digital dv dd 3318 input: digital video input/osd input (pull down if not used) output: video decoder output 2[5] (bt.656) 119 dcrin6 i/o h cmos digital dv dd 3318 input: digital video input/osd input (pull down if not used) output: video decoder output 2[6] (bt.656) 120 dcrin7 i/o h cmos digital dv dd 3318 input: digital video input/osd input (pull down if not used) output: video decoder output 2[7] (bt.656)
LC74900 no.a2000-11/14 pin type i/o type function equivalent circuit applicable pins a schmitt trigger cmos input xrst,xpdwn,scs_i2sel,xmute b 8ma 3-state drive cmos i/o gp0,gp1,gp2,stxd,into, drout0,drout1,drout2,drout3, drout4,drout5,drout6,drout7, dbout0,dbout1,dbout2,dbout3, dbout4,dbout5,dbout6,dbout7, dgout0,dgout1,d gout2,dgout3, dgout4,dgout5,d gout6,dgout7 dvso,dhso,ddeo,dexr, pwm,pol,sp,strb, cpv,oe,flm,grst c 8ma opendrain output cmos input* sck_scl,srxd_sda d cmos input siosel,mode2,mode3,test,mode0, dcki,mode1,ddei,dvsi,dhsi, dcbin0,dcbin1,dcbin2,dcbin3, dcbin4,dcbin5,dcbin6,dcbin7, dygin0,dygin1,dygin2,dygin3, dygin4,dygin5,dygin6,dygin7 e analog i/o refpkv,vrt,refnkv,vrb,ain4, ain3,ain2,ain1,svo,lpfo f oscillator circuit i/o xtali,xtalo g 12ma 3-state drive cmos output dcko1 h 3.3v: 8ma 1.8v: 3ma 3-state drive cmos i/o dcrin0,dcrin1,dcrin2,dcrin3, dcrin4,dcrin5,dcrin6,dcrin7 j 3.3v: 12ma 1.8v: 5ma 3-state drive cmos output dcko2
LC74900 no.a2000-12/14 i/o data timing (1) input data timing pin name parameter symbol min typ max unit clock cycle t ck 16.7 ns dcki duty 50 % input data setup time (dv dd 33 = 3.15v to 3.45v) (dv dd 3318 = 3.15v to 3.45v) t su 3 ns dcrin*, dygin*, dcbin*, dvsi, dhsi, ddei input data hold time (dv dd 33 = 3.15v to 3.45v) (dv dd 3318 = 3.15v to 3.45v) t hd 2 ns * the recommended duty ratio of input clock is 50% (2) output data timing pin name parameter symbol min typ max unit clock cycle t ck 16.7 ns dcko1 duty 50 % drout*, dgout*, dbout* dvso, dhso, ddeo, dexr, pol, sp, strb, cpv, oe, flm, grst output data delay time dv dd 33 = 3.15v to 3.45v t ac -3 3 ns * dcko1 output is not inverted. output capacitance: 15pf pin name parameter symbol min typ max unit clock cycle t ck 37 ns dcko2 duty 50 % dcrin*, dexr, pol, sp strb, cpv, oe, flm, grst, gp0, gp1, dvso, dhso output data delay time dv dd 3318 = 3.15v to 3.45v dv dd 33 = 3.15v to 3.45v t ac -3 3 ns dcrin* output data delay time dv dd 3318 = 1.7v to 1.9v t ac -6 6 ns * dcko1 output is not inverted. output capacitance: 15pf t lo t ck t ac dcko2 output data dv dd 3318/2 dv dd 3318/2 t ho t lo t ck t ac dcko1 output data dv dd 33/2 dv dd 33/2 t ho dv dd 33/2 t hi t li t ck t su t hd dcki dv dd 33/2 in p ut data
LC74900 no.a2000-13/14 connection example of parallel out put mode (panel/video decoder) * for details, see application note. digital power supply ain1 adc connection (power supply, filter, etc.) ain2 ain3 ain4 svo tcon cvbs input (4 to 1 select) adc0av dd 33 adc1av dd 33 adc0av ss 33 adc1av ss 33 lpfo grst fml oe cpv strb sp pol dexr refpkv vrt vrb refnkv dcko1 ddeo dvso dhso dcko2 video decoder output itu-r bt.656 8bit mute control (active low level) reset (active low level) dcrin0-7 dcbin0-7 digital video rgb 18bit input operation mode control dygin0-7 gp0 gp1 dcki ddei dvsi dhsi test mode3 i 2 c bus interface mode2 mode1 mode0 siosel gp2 scs_i2sel stxd xmute xrst xpdwn xtali 27mhz fundamental crystal oscillator cl1 cl2 xtalo srxd_sda sck_scl 8 ferrite open open cvbs agnd agnd agnd dgnd dgnd rd a3.3v 0.1 f 0.1 f 0.1 f 10 f 10 f into pwm ferrite d3.3v or 1.8v d3.3v d1.5v ferrite ferrite dgnd agnd 8 8 sync clock output interrupt output lcd backlight control panel output (r) (*)if 6bit outputs, drout1-0 is opened drout0 drout1 drout2 drout3 drout4 drout5 drout6 drout7 panel output (b) (*)if 6bit outputs, drout1-0 is opened dbout0 dbout1 dbout2 dbout3 dbout4 dbout5 dbout6 dbout7 panel output (g) (*)if 6bit outputs, drout1-0 is opened dgout0 dgout1 dgout2 dgout3 dgout4 dgout5 dgout6 dgout7 dv dd 3318 dv dd 33 dv dd 15 pllav dd 33 pdo pllav ss 33 dv ss 33 ferrite a3.3v d3.3v d3.3v pll connection (power supply, etc.)
LC74900 ps no.a2000-14/14 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of march, 2012. specifications and information herein are subject to change without notice.

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